CSFutureIB · IB DP Computer Science 2027
A1.1.1 · CPU Components SL + HL 📄 Paper 1
Theme A › A1 Computer Fundamentals › A1.1 Computer Hardware and Operation

Inside the CPU:
Components & Interaction

By the end, you will be able to identify CPU components, explain their roles, and trace how they interact during instruction processing — exactly what Paper 1 tests.

The CPU Is Not One Magic Box

Section 01

The Central Processing Unit looks simple from the outside — but inside it is a carefully coordinated system. Every instruction you run goes through multiple dedicated components, each with a precise role. Understanding this structure is exactly what IB Paper 1 tests.

📍
Address fetched
PC → MAR
→
📥
Memory accessed
MAR → MDR
→
🔍
Decoded
MDR → CIR → CU
→
⚙️
ALU operates
CU → ALU
→
💾
Result stored
→ Accumulator
📌 Paper 1 relevance: A1.1.1 is high-frequency. Expect questions on register roles, bus types, and the fetch-decode-execute cycle. The command terms are: state (1 mark), outline (2 marks), explain (4 marks), distinguish (4 marks).

Inside the CPU: Click the Components

Section 02

Click any component to see its role, what it stores, and an IB exam phrase you can use directly in Paper 1 answers.

Select a component above
Click any CPU component to see its role, what it stores or controls, and a ready-to-use IB exam phrase.

Core Vocabulary Lab

Section 03

Click any term to expand its full definition, role in the CPU, and IB exam relevance.

ALU
Performs arithmetic and logical operations.
The Arithmetic Logic Unit carries out calculations (add, subtract, multiply) and logical comparisons (AND, OR, NOT, greater than). It does not decide which operation to run — the Control Unit signals it. Results are stored in the accumulator.

IB phrase: "The ALU performs arithmetic and logical operations on data."
Control Unit
Coordinates all CPU activity — the conductor.
The Control Unit decodes instructions from the CIR and sends signals to other components (ALU, memory, registers, buses) to coordinate the fetch-decode-execute cycle. It does not perform calculations itself.

IB phrase: "The Control Unit directs the flow of data between CPU components and coordinates the fetch-decode-execute cycle."
Register
Ultra-fast internal CPU storage location.
Registers are the fastest memory in the computer system — they are built directly inside the CPU. Each register holds a small specific piece of data (an address, an instruction, or a value). They are much faster than RAM but very limited in number.

IB phrase: "Registers provide fast temporary storage within the CPU for addresses, instructions, and data."
Accumulator
Stores intermediate results from ALU operations.
The accumulator is a special register that holds the result of the most recent ALU operation. When the ALU adds 8 + 3, the result 11 is placed in the accumulator. It is used as an input for subsequent calculations.

IB phrase: "The accumulator stores the result of arithmetic and logical operations performed by the ALU."
Program Counter
Stores address of the next instruction.
The PC holds the memory address of the next instruction to be fetched. After each fetch, the PC is automatically incremented to point to the next instruction. It keeps the CPU working through the program in sequence.

IB phrase: "The Program Counter stores the memory address of the next instruction to be fetched."
MAR
Memory Address Register — holds the address being accessed.
The MAR receives the address from the PC and holds it while memory is being accessed. It is connected to the address bus. The MAR always stores a memory address — never data itself.

IB phrase: "The MAR stores the memory address of the location currently being read from or written to."
MDR / MBR
Stores data being transferred between CPU and memory.
The Memory Data Register (also called Memory Buffer Register) temporarily holds the data or instruction that has just been fetched from memory, or data that is about to be written to memory. It is connected to the data bus.

IB phrase: "The MDR stores the data or instruction fetched from the memory location specified by the MAR."
CIR / IR
Holds the instruction currently being decoded and executed.
The Current Instruction Register (or Instruction Register) receives the instruction from the MDR and holds it while the Control Unit decodes and executes it. Only one instruction is in the CIR at a time.

IB phrase: "The CIR holds the current instruction while it is being decoded by the Control Unit."
Bus
Shared communication pathway between components.
A bus is a set of parallel wires that carry data, addresses, or control signals between CPU, memory, and I/O devices. There are three types: address bus, data bus, and control bus — each carrying different information in different directions.

IB phrase: "Buses provide the communication pathways through which CPU, memory, and peripherals exchange data, addresses, and control signals."
Clock
Sets the tempo of all CPU operations.
The system clock generates regular pulses that synchronise all CPU operations. Each pulse triggers the next step in the fetch-decode-execute cycle. Clock speed is measured in GHz (gigahertz). A faster clock can perform more operations per second, but heat and power consumption are constraints.

IB phrase: "The clock synchronises CPU operations; a higher clock speed allows more instructions to be executed per second."

Match the Register to Its Job

Section 04

Click a register on the left, then click its matching role on the right. Complete all five pairs correctly.

Registers
Roles
Quick CheckIdentify Register
Which register holds the memory address of the instruction currently being accessed?

How Data Travels: The Three Buses

Section 05

The CPU and memory communicate through three different bus types — each carrying different information. Click each action to see which bus activates and why.

CPU ↔ Memory Bus Simulator
🖥️
CPU
Address Bus→
Data Bus↔
Control Bus↔
🗃️
Memory
Click an action below to see which bus activates and what it carries.
Quick CheckIdentify Bus
The CPU needs to tell memory which location to read from. Which bus carries this information?

Follow One Instruction Through the CPU

Section 06

Trace the instruction ADD 5 from memory all the way to the accumulator. This is the fetch-decode-execute cycle in action.

Instruction Journey SimulatorStep-by-step
Press Start to trace the instruction ADD 5 through all CPU components.
CPU Registers
Program Counter (PC)
—
MAR
—
MDR
—
CIR
—
Control Unit
—
ALU
—
Accumulator
—
Memory
0x100ADD 5
0x101STORE 0x200
0x102HALT
← Current instruction at 0x100
Click Start to begin the instruction trace. Each step shows exactly what happens to each register and why.
Quick CheckInstruction Cycle
What happens to the Program Counter immediately after the address is copied to the MAR?

What Does the ALU Actually Do?

Section 07

The ALU performs two categories of operation: arithmetic (calculations) and logical (comparisons and bitwise). Select values and an operation to see the result.

ALU Operation Playground
Select an operation above.
Accumulator
—
The ALU receives two inputs and a signal from the Control Unit specifying which operation to perform. The result is placed in the accumulator.

The ALU handles both arithmetic (add, subtract, multiply) and logical (AND, OR, compare) operations.
⚠ Important: The ALU does not decide which operation to perform — the Control Unit sends that signal. The ALU simply executes it.

The Control Unit: The CPU's Coordinator

Section 08

The Control Unit is the conductor of the CPU. It does not calculate anything itself — it reads the instruction in the CIR and signals every other component to do their jobs.

Control Unit Command Centre
Control Unit
Reads CIR → sends signals
Click a command button to see what the Control Unit signals and which components it activates.
Quick CheckControl Unit Role
True or False: The Control Unit performs the actual arithmetic operations in the CPU.

One Core or Many Cores?

Section 09

Modern processors contain multiple cores — each core is essentially an independent processing unit. More cores can help with some tasks but not all.

Single-core vs Multi-core Comparator
Single-Core
C1
Multi-Core (4 cores)
C1
C2
C3
C4
Select a task scenario to see how single-core and multi-core processors compare.
Quick CheckMulti-core
A student claims: "A quad-core processor always runs programs exactly 4× faster than a single-core processor." Is this correct?

Specialist Helpers: Co-processors

Section 10

A co-processor is a specialised processor designed to handle a specific type of task more efficiently than the general-purpose CPU. For each scenario, decide whether the CPU, a co-processor, or both would handle it.

IB Exam Lens

Section 11
🎯 Paper 1 Command Terms for A1.1.1

Every Paper 1 answer must match the command term. Here is exactly what each requires for CPU questions:

state Name/define in one sentence — no elaboration needed. outline Brief description with one key detail. describe What it does + how it does it. explain Role + how it works + why it matters in context. distinguish Compare both terms — difference must be explicit.
📝 Ready-to-use exam phrases:
"The ALU performs arithmetic and logical operations on data…"
"The Control Unit coordinates the fetch-decode-execute cycle…"
"The Program Counter stores the address of the next instruction to be fetched…"
"The MAR stores the address of the memory location being accessed…"
"The MDR stores the data or instruction transferred between CPU and memory…"
"The address bus carries memory addresses, whereas the data bus carries data or instructions…"
1
Confusing CU and ALU roles
Writing "the Control Unit performs calculations" or "the ALU controls components" are both wrong and common errors.
Fix: CU = coordinator/conductor. ALU = calculator. They never swap roles.
2
Confusing MAR and MDR
MAR holds an ADDRESS. MDR holds DATA. Writing the wrong one in a sequence answer loses marks.
Fix: MAR = address register (connected to address bus). MDR = data register (connected to data bus).
3
Saying the address bus is two-way
The address bus is unidirectional — it only goes from CPU to memory. The data bus is bidirectional.
Fix: Address bus → (CPU to memory, one-way). Data bus ↔ (both directions).
4
Saying more cores always = more speed
Multi-core only helps when tasks can be divided. Sequential tasks see little or no benefit.
Fix: Always qualify — "multi-core improves performance when tasks can be parallelised."

CPU Misconception Detective

Section 12

Five common hardware misconceptions. For each, click the correct problem type to reveal the IB-accurate correction.

Build a Paper 1 CPU Answer

Section 13
📝 Answer Builder — 4-mark Explain Question
Explain how the Program Counter, MAR, MDR, and CIR are used when fetching an instruction from memory.
[4 marks]
Select answer points (click all relevant):
Select points above to build your model answer.
✓
PC role explained
✓
MAR role explained
✓
MDR role explained
✓
CIR role explained
✓
Sequence is logical
📝 Answer Builder — 4-mark Distinguish Question
Distinguish between the address bus and the data bus.
[4 marks]
Select points for both sides:
Select points above to build your model answer.
✓
Address bus purpose stated
✓
Data bus purpose stated
✓
Directionality difference noted
✓
Example included

Final Practice Zone

Section 14
Short · State[1 mark]
State the role of the ALU.
Markscheme
  • [1] The ALU (Arithmetic Logic Unit) performs arithmetic and logical operations on data.
Examiner: Must mention BOTH arithmetic AND logical operations. "Performs calculations" alone earns 0.
Short · State[1 mark]
State the role of the Program Counter.
Markscheme
  • [1] The Program Counter stores the memory address of the next instruction to be fetched.
Examiner: Must reference "address" and "next instruction." Saying "stores the current instruction" is wrong (that is the CIR).
Short · Outline[2 marks]
Outline the role of the accumulator in the CPU.
Markscheme
  • [1] The accumulator is a register that stores the result of the most recent ALU operation.
  • [1] It holds intermediate results and can be used as an input for subsequent operations.
Examiner: Must link to ALU. "Stores results" without "from the ALU" earns 0 for the first mark.
Short · State[1 mark]
State one reason why registers are faster than main memory (RAM).
Markscheme
  • [1] Registers are located inside the CPU itself, so there is no need to communicate across buses to access them / they are accessed directly without a memory access cycle.
Accept: smaller capacity means faster lookup; built from faster flip-flop technology; on-chip location eliminates bus latency.
Medium · Distinguish[4 marks]
Distinguish between the MAR and MDR.
Markscheme
  • [1] The MAR (Memory Address Register) stores the address of the memory location currently being accessed.
  • [1] The MDR (Memory Data Register) stores the data or instruction that has been fetched from that memory location, or data to be written to memory.
  • [1] The MAR is connected to the address bus; the MDR is connected to the data bus.
  • [1] The MAR holds a location; the MDR holds the contents of that location — for example, MAR = 0x100, MDR = ADD 5.
Examiner: Distinguish requires BOTH sides. Describing only MAR or only MDR earns maximum 2 marks.
Medium · Explain[4 marks]
Explain why a multi-core processor may not always improve performance.
Markscheme
  • [1] A multi-core processor has multiple processing units that can execute tasks simultaneously (in parallel).
  • [1] Performance improvement depends on whether the task can be divided into independent sub-tasks that run on different cores.
  • [1] If a task is sequential (each step depends on the result of the previous step), additional cores cannot help and performance may not improve significantly.
  • [1] There is also overhead in coordinating cores and dividing tasks, which can reduce the theoretical speed gain. For example, rendering a 3D scene benefits from multiple cores, whereas a single calculation that must be computed in order does not.
Examiner: Must mention parallelisation/sequential dependency. Generic "not all programs use all cores" without explanation earns 1 mark only.
Extended · Explain[6 marks]
Explain how the CPU components interact when fetching and executing the instruction ADD 5 stored at memory address 0x100.
Markscheme
  • [1] The Program Counter (PC) contains 0x100, the address of the next instruction to be fetched.
  • [1] This address is copied from the PC to the MAR, and the PC is incremented to 0x101 ready for the next instruction.
  • [1] The Control Unit sends a memory read signal via the control bus; the instruction ADD 5 at address 0x100 is sent from memory to the MDR via the data bus.
  • [1] The instruction is copied from the MDR to the CIR, where it is held while the Control Unit decodes it.
  • [1] The Control Unit interprets ADD 5 and sends signals to the ALU to perform an addition. The value 5 is retrieved and the ALU performs the addition (e.g. accumulator + 5).
  • [1] The result is stored in the accumulator; the cycle then repeats for the next instruction at the address now in the PC.
Examiner: Award one mark per logical step. Must name the component AND describe what it does. Marking should be lenient on order as long as the sequence is logically coherent.
Quick CheckSequence Check
In the fetch-decode-execute cycle, which component receives the instruction LAST before it is decoded?

IA Connection

Section 15
🔬 Internal Assessment — Computational Solution

Hardware Awareness in Your IA

Understanding CPU architecture helps you make better decisions in your IA computational solution. IB examiners reward evidence of hardware-aware thinking in Criterion D (Development) and Criterion B (Design).

⚡ Algorithm Efficiency

Choosing an O(n log n) sort over O(n²) directly reduces the number of ALU operations. If your IA runs on limited hardware, justify algorithm choices with CPU operation counts.

🌐 Local vs Cloud Processing

Understanding bus latency and memory access helps justify why local processing (on-device) can be faster than sending data to a server — relevant for IA systems handling real-time data.

💾 Storage Justification

In your design rationale, you can justify why RAM is used for active data (fast register access) versus why data is persisted to disk — linking hardware awareness to your design decisions.

Summary Checklist

Section 16

✔ You are ready for A1.1.2 if you can…

  • Identify and state the role of: ALU, Control Unit, Accumulator, PC, MAR, MDR, CIR, and buses
  • Explain the difference between the address bus, data bus, and control bus — including direction
  • Trace the fetch-decode-execute cycle through each CPU component in the correct sequence
  • Distinguish MAR (stores address) from MDR (stores data) without confusion
  • Explain why multi-core processors do not always improve performance for every task
  • Write a 4-mark "explain" answer on the fetch cycle using all four key registers
  • Write a 4-mark "distinguish" answer comparing address bus and data bus
You have completed A1.1.1 — CPU Components and How They Interact
Coming next

A1.1.2 — The Role of the GPU

You now understand how the CPU works and why co-processors exist. Next, you will explore the Graphics Processing Unit — a specialist co-processor with thousands of small cores designed for parallel computation. Its architecture directly connects to everything you learned here about multi-core processing.

→